Cool In The Spotlight
QuickLogic Focuses on Low Power

QuickLogic knows who you are. They’re here to help. First you need to admit that you have a problem. Maybe you’re the one that just finished the second revision of your Mobile-Super-Franistan only to be told by the “marketing” people that the next version needs to be the “Wi-Fi enabled Mobile-Super-Franistan. (You know the marketing people, they’re the ones down the hall that don’t wear jeans and Land’s End shirts to work - the ones that put animation in their PowerPoint presentations until they found out it was geeky…)” Well, Wi-Fi shouldn’t be a problem, right? There are chipsets for that. However, in the last round of cost reduction, you decided to pull out the PCI and go with a proprietary bus. Now you need something to bridge the gap to the PCI interface on the Wi-Fi, buffer data, and not use any power at all, because you’re already near your power budget with the addition of the 802.11.

QuickLogic’s recently announced Eclipse II super-low-power antifuse FPGA family is another worthy attempt at changing the rules and the perceptions of FPGAs. While FPGAs have a reputation for being low-speed, high-power, volatile devices, Eclipse II has none of these properties. Eclipse II offers a density range that’s clearly in FPGA territory (ranging from about 50K to over 300K system-gates). It is non-volatile, very fast (over 300MHz 16-bit counter performance), and extremely low power, with 0.17µA standby current and impressively low dynamic power. In addition, Eclipse II has other FPGA-like features, such as embedded RAM, that clearly differentiate it from popular CPLD families.

QuickLogic took a careful look at the market and realized that there was a gaping hole in the area of high-capability FPGAs with ultra-low power consumption. Because of their high-power heritage, FPGAs have traditionally been barred from most applications that run on batteries, have power-supply limitations, or have trouble with heat dissipation. As a result, the only options left for many design teams were costly ASIC designs, low-density CPLDs with accompanying memory, or Rube Goldbergian arrangements of ASSPs and standard parts with bits of customized logic in PLDs and separate RAM. [more]